• 专利附录
  • 专利说明
  • 权利要求
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    • 专利摘要:
    The invention relates to a control circuit (100) for ultrasonic transducers (TD1, TDn) configurable according to the type of transducer to be controlled, this circuit comprising a first terminal (b) intended to be connected to a first electrode (E1) of each of the transducers (TD1, TDn), and a bias switch (SWp) configurable to connect the first terminal (b) to either one of the first (P1) and second (P2) polarization nodes as a function of the type of transducers to order.
    公开号:FR3061616A1
    申请号:FR1750071
    申请日:2017-01-04
    公开日:2018-07-06
    发明作者:Pascal CHATAIN；Mathieu Roy；Etienne FLESCH；Edgard Jeanne
    申请人:Moduleus；
    IPC主号:
    专利说明:

    Holder (s): trusted.
    MODULEUS simpliO joint stock company Extension request (s):
    ® Agent (s): CABINET BEAUMONT.
    ® ULTRASONIC TRANSDUCER CONTROL CIRCUIT.
    FR 3,061,616 - A1 (® The invention relates to a control circuit (100) for ultrasonic transducers (TD 1 , TD n ) configurable as a function of the type of transducers to be controlled, this circuit comprising a first terminal (b) intended for be connected to a first electrode (E1) of each of the transducers (TD- |, TD n ), and a polarization switch (SWp) configurable to connect the first terminal (b) to either of the first ( P1) and second (P2) polarization nodes depending on the type of transducers to be controlled.

    B15246
    CONTROL CIRCUIT FOR ULTRASONIC TRANSDUCERS
    Field
    The present application relates to the field of ultrasound imaging, and relates more particularly to an electronic circuit for controlling ultrasound transducers of an ultrasound imaging system.
    Presentation of the prior art
    An ultrasound imaging system conventionally comprises a plurality of ultrasound transducers, for example arranged in a strip or in a matrix. In operation, all of the transducers are arranged facing a body of which it is desired to acquire an image. The system further comprises an electronic control circuit adapted to apply electrical excitation signals to the transducers, so as to cause the emission of ultrasonic waves by the transducers. The ultrasonic waves emitted by the transducers are reflected by the body to be analyzed (by its internal and / or surface structure), then return to the transducers which again convert them into electrical signals. These electrical response signals are read by the electronic control circuit, and can be memorized and analyzed to deduce therefrom information on the body studied.
    B15246
    Traditional ultrasound imaging systems are relatively complex and expensive systems, used for example in the medical field (ultrasound) or for industrial applications (non-destructive testing of materials). More recently, applications intended for the general public have been proposed, for example biometric applications, in which a sensor with ultrasonic transducers is used to acquire a biometric signature of a user, for example a fingerprint. Compared to optical type biometric sensors, an advantage is an improvement in the reliability of identification linked in particular to the integration of information regarding the internal structure of the member (finger, palm, etc.) used for identification .
    It would be desirable to be able to at least partially improve certain aspects of existing ultrasound imaging systems. In particular, it would be desirable to be able to reduce the cost of such systems, and in particular the cost linked to the electronic circuit for controlling the transducers. This is particularly important for applications intended for the general public, in which the cost of the electronic circuit for controlling the transducers can represent a significant part of the total cost of the system.
    summary
    Thus, one embodiment provides a control circuit for ultrasonic transducers, characterized in that it is configurable as a function of the type of transducers to be controlled.
    According to one embodiment, the control circuit comprises a first terminal intended to be connected to a first electrode of each of the transducers, and a polarization switch configurable to connect the first terminal to either of the first and second polarization nodes depending on the type of transducers to be controlled.
    According to one embodiment, the first bias node is an output node of a circuit for supplying a DC bias voltage, and the second node
    B15246 polarization is a node for applying a reference potential of the circuit.
    According to one embodiment, the circuit for supplying a DC bias voltage comprises a DC-DC voltage converter configurable to modify the level of the bias voltage which it delivers.
    According to one embodiment, the control circuit comprises a plurality of second terminals intended to be connected respectively to second electrodes of the transducers to be controlled.
    According to one embodiment, the control circuit comprises a plurality of voltage pulse generators, each of the second terminals being connected to one of the voltage pulse generators.
    According to one embodiment, the voltage level of the voltage pulses delivered by the pulse generators is configurable.
    According to one embodiment, the control circuit further comprises a reception circuit comprising an input node, a reception amplifier whose input is connected to the input node, an analog-digital converter whose input is connected to the output of the receiving amplifier, and an output connected to the output of the analog to digital converter.
    According to one embodiment, the control circuit comprises a plurality of switches respectively connecting the second terminals to the input node of the reception circuit.
    According to one embodiment, the reception circuit comprises an impedance matching circuit configurable as a function of the type of transducers to be controlled.
    According to one embodiment, the reception circuit further comprises, between the reception amplifier and the analog-digital converter, at least one of the following elements:
    an analog gain adjustment circuit; and
    B15246 an analog anti-aliasing filter.
    According to one embodiment, the reception circuit comprises a network of switched capacities disposed upstream of the analog-digital converter, making it possible to store analog samples representative of the output signal of the reception amplifier, before their digitization by the converter analog-digital.
    Brief description of the drawings
    These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments made without implied limitation in relation to the attached figures among which:
    FIG. 1 is a simplified electrical diagram illustrating an example of an embodiment of an electronic circuit for controlling ultrasonic transducers;
    Figure 2 is an electrical diagram illustrating in more detail an embodiment of a pulse generator of the control circuit of Figure 1;
    Figure 3 is an electrical diagram illustrating in more detail another embodiment of a pulse generator of the control circuit of Figure 1;
    FIGS. 4A, 4B and 4C are electrical diagrams illustrating in more detail three alternative embodiments of a reception amplifier of the control circuit of FIG. 1; and FIG. 5 is an electrical diagram illustrating an alternative embodiment of a reception circuit of the control circuit of FIG. 1.
    detailed description
    The same elements have been designated by the same references in the different figures. For the sake of clarity, only the elements which are useful for understanding the embodiments described have been shown and are detailed. In particular, the various applications which the described control circuit may have have not been detailed, the modes of
    B15246 described embodiment being compatible with the usual applications of ultrasound imaging systems. In addition, the properties (frequencies, shapes, amplitudes, etc.) of the electrical excitation signals applied by the control circuit to the ultrasonic transducers have not been detailed, the embodiments described being compatible with the excitation signals usually used in ultrasound imaging systems, which can be chosen according to the application considered and in particular the nature of the body to be analyzed and the type of information that one seeks to acquire.
    In the present description, the term connected is used to denote a direct electrical connection, without an intermediate electronic component, for example by means of one or more conductive tracks or conductive wires, and the term coupled or the term connected, to denote a link. electrical which can be direct (meaning then connected) or indirect (i.e. via one or more intermediate components).
    In existing ultrasonic imaging systems, the electronic transducer control circuit is a circuit specifically designed for the application considered, and in particular depending on the type of transducers used. Indeed, there are different technologies of ultrasonic transducers, for example piezoelectric transducers, crystal transducers, CMUT transducers (capacitive membrane transducers), etc. According to the chosen technology, and / or, for a given technology, according to the dimensions of the transducers, the constraints on the control circuit may be different, in particular with regard to the power of the excitation signals applied to the transducers, the level of the bias voltage applied to the transducers, and / or the adaptation d impedance between the transducers and the circuits for reading the electrical response signals produced by the transducers.
    Providing a specific control circuit for each ultrasound imaging application translates into costs
    B15246 significant development, and therefore by a relatively high cost price of the control circuit.
    According to one aspect of an embodiment, an ultrasound transducer control circuit is provided which can be configured or configured as a function of the type of transducers to be controlled. Such a circuit has the advantage of being able to be used for different applications, and in particular for controlling transducers of different technologies and / or having different dimensions. This eliminates the need to develop a specific control circuit for each ultrasound imaging application, and thus to achieve economies of scale.
    FIG. 1 is a simplified electrical diagram illustrating an example of an embodiment of an electronic control circuit 100 of ultrasonic transducers. In Figure 1, in addition to the control circuit 100, there are shown n ultrasonic transducers TD] _, ..., TD n to be controlled, where n is an integer greater than 1, for example between 10 and 5000, as well as 'a polarization capacitor Cp. The TDj_,. . ., TD n of the system of FIG. 1 are for example identical to the manufacturing dispersions. By way of example, the transducers TD] _, ..., TD n are piezoelectric transducers, crystal transducers, or CMUT transducers. Each TDy ultrasonic transducer, with i integer ranging from 1 to n, comprises two electrodes E1 and E2. When an appropriate excitation voltage is applied between the electrodes E1 and E2, the transducer emits an ultrasonic acoustic wave. When the transducer receives an ultrasonic acoustic wave in a certain frequency range, it supplies between its electrodes E1 and E2 a voltage representative of the received wave.
    The circuit 100 includes n terminals aj_, ..., a n , intended to be connected respectively to the electrodes E2 of the transducers TDj_,. . ., TD n . The circuit 100 further comprises a single terminal b intended to be connected to the electrodes El of the transducers TDj_,
    B15246
    ... TD n . In the example shown, the electrodes E2 of the transducers TD] _, ..., TD n are connected respectively to the terminals aj_, ..., a n of the control circuit 100, and the electrodes El of the transducers TD] _, ..., TD n are connected to terminal b of the control circuit 100.
    The polarization capacitor Cp of the system of FIG. 1 connects the terminal b of the circuit 100 to a node GND of application of a reference potential of the system, for example the ground. In the example shown, the capacitor Cp is external to the circuit 100. As a variant, the capacitor Cp can be included in the circuit 100.
    The control circuit 100 of FIG. 1 comprises, for each ultrasonic transducer TD-j_, a pulse generator TX-j_ and a controllable switch SWTX-j_ connecting an output node out of the pulse generator TX-j_ to the terminal a-j_ of the circuit coupled to the electrode E2 of the transducer TD-j_. The pulse generators TXj_, ... TX n associated with the various transducers are for example identical to the manufacturing dispersions. In addition, the switches SWTX] _, ..., SWTX n can be identical to the manufacturing dispersions. Each TX-j_ pulse generator comprises an input node which is not adapted to receive a logic control signal. When the logic signal applied to the input node in of the generator TX-j_ is in a first state, the generator TX-j_ supplied on its output node out of a high level voltage + HV, and, when the logic signal applied on the node in of the TX-j_ generator is in a second state, the generator TX-j_ supplied on its output node with a low level voltage -HV. By way of example, the voltages + HV and -HV are respectively positive and negative with respect to the reference voltage of the circuit applied to the node GND. As a variant, the voltage -HV is equal to the reference voltage of the circuit, and the voltage + HV is positive with respect to the reference voltage of the circuit. The output signal from the pulse generator TX-j_ corresponds to an excitation signal from the transducer TD-j_, which can be applied to the electrode E2 of the
    B15246 TD-j_ transducer via the SWTX j_ switch. The voltage level of this excitation signal is relatively high, for example of the order of 10 to 50 volts peak to peak (that is to say between the low level -HV and the high level + HV). In the example of FIG. 1, the circuit 100 comprises a DC-DC voltage converter 101 (DC / DC), adapted to generate, from a supply voltage (not shown) of the circuit 100, for example between 1 and 5 volts, the supply voltages + HV, and, if necessary, -HV of the pulse generators TX-j_. Preferably, the DC-DC converter 101 is configurable to modify the level of the output voltages + HV, and, where appropriate, -HV delivered, which makes it possible to make the circuit 100 compatible with different types of ultrasonic transducers adapted to receive different levels of excitation voltage. In the example shown, the DC-DC converter 101 is a single converter shared by the various pulse generators TX-j_. Alternatively, each TX-j_ pulse generator can be coupled to its own DC-DC converter.
    The control circuit 100 of FIG. 1 further comprises a logic control circuit 103 (CTRL) connected to the input nodes in of the various pulse generators TX-j_. The control circuit 103 is adapted to apply logic control sequences to the various pulse generators. The circuit 103 can individually control the various pulse generators TX] _, ..., TX n , simultaneously or sequentially. The control circuit 103 comprises for example one or more digital processing or conditioning circuits (not detailed), for example of the microprocessor or programmable logic circuit type (for example FPGA), and one or more memory circuits (not detailed). The control circuit 103 is for example adapted to memorize a plurality of scenarios of excitation of the predetermined transducers, corresponding for example to distinct excitation frequencies, and which can be selected by
    B15246 the user according to the envisaged application, and in particular according to the type of transducers used, and / or according to the type of body to be analyzed, and / or according to the type of image or information sought . In the case where the DC-DC converter 101 is configurable, the latter can for example be configured via the control circuit 103, via a configuration link not shown.
    The electronic control circuit 100 of FIG. 1 further comprises a reception circuit 105 adapted to amplify and digitize the electrical response signals generated by the ultrasonic transducers. The circuit 100 of FIG. 1 further comprises n controllable switches SWRX] _, ..., SWRX n , respectively connecting the terminals aj_, ..., a n to an input node c of the reception circuit 105. The reception circuit 105 comprises a reception amplifier 107, preferably low noise (LNA), the input of which is connected to node c, and an analog to digital converter 109 (ADC), the input of which is connected to the output of the amplifier 107 and the output of which is connected to an output d (on several bits) of the reception circuit 105. The output d of the reception circuit 105 is connected to the control circuit 103. By way of example, the converter 109 is suitable for providing, on the output d, digital samples quantized on 8 to 24 bits, for example on 14 bits, representative of the amplitude of the input signal of the converter, at a digitization frequency between 50 and 250 MHz , for example at a frequency of 120 MHz.
    In the example of FIG. 1, the reception circuit 105 further comprises, between the node c and the input of the amplifier 107, an impedance matching circuit 111 allowing, if necessary, adapt the input impedance of the amplifier 107 to the impedance of the ultrasonic transducers. Preferably, the impedance matching circuit 111 is configurable, which makes it possible to make the circuit 100 compatible with different types of ultrasonic transducers having different impedances. For example, the circuit
    B15246 impedance matching 111 includes a configurable network of resistors and / or capacitors. In the case where the impedance matching circuit 111 is configurable, the latter can for example be configured via the control circuit 103, via a configuration link not shown.
    In the example of FIG. 1, the reception circuit 105 further comprises, between the output of the amplifier 107 and the input of the analog-digital converter 109, a gain adjustment circuit (VGA) 113. The circuit 113 is for example digitally controllable by the control circuit 103. The circuit 113 makes it possible to apply a variable gain to the output signal of the amplifier 107 during a phase of reading the return signal received by an ultrasonic transducer . By way of example, during a reading phase of the return signal received by an ultrasonic transducer, the control circuit 103 controls the circuit 113 to progressively increase the gain applied to the output signal of the amplifier 107. Indeed, during a reception phase of an ultrasonic signal reflected by the body to be analyzed, the amplitude of the reflected signal decreases over time, insofar as, the more time passes, the greater the distance traveled by the reflected signal , and the more the reflected signal is attenuated. The progressive increase in the gain applied by the adjustment circuit 113 makes it possible to maximize the amplitude of the signal applied at the input of the analog-digital converter 109, and therefore to minimize the quantization noise introduced by the converter 109.
    In the example of FIG. 1, the reception circuit 105 further comprises an analog anti-aliasing filter 115 (AAF), for example a low pass filter, disposed between the output of the amplifier 107 and the input of the analog to digital converter. 109. In the example shown, the filter 115 is arranged between the output of the gain adjustment circuit 113 and the input of the converter 109.
    The control circuit 100 of FIG. 1 further comprises a polarization switch SWp, configurable for connecting
    B15246 the node b either at a first polarization node PI or at a second polarization node P2, depending on the type of transducers TD-j_ connected to the control circuit 100. The switch SWp can for example be controlled by one intermediary of the control circuit 103.
    In the example of FIG. 1, the node PI is an output node of a circuit 117 for supplying a DC bias voltage Vp-i_ as , for example a positive voltage with respect to the reference voltage or ground of the circuit. By way of example, the bias voltage Vp-i_ as is between 5 and 200 V, for example of the order of 30 V. Such a bias voltage is very particularly suitable for CMUT type transducers. Thus, when the circuit 100 is used to control transducers of the CMUT type, the switch SWp can be configured to connect the node b to the node PI. The circuit 117 is for example a DC-DC voltage converter (DC / DC), adapted to generate the bias voltage Vpj_ as from a supply voltage (not shown) of the circuit 100, for example between 1 and 5 volts. Preferably, the circuit 117 is configurable to modify the level of the bias voltage Vp-i_ as delivered, which makes it possible to make the circuit 100 compatible with different types of ultrasonic transducers adapted to receive different levels of bias voltage, or , for a given type of transducer, to modify the mechanical-electrical conversion coefficient of the transducer. In the case where the circuit 117 is configurable, the latter can for example be configured via the control circuit 103.
    In the example of FIG. 1, the node P2 is connected to the reference node or GND ground of the circuit. The switch SWp can be configured to connect node b to node P2 when the circuit 100 is used to control ultrasonic transducers of the piezoelectric or crystal type, insofar as these transducers do not need to be polarized.
    B15246
    By way of example, the various components of the control circuit 100 of FIG. 1 can be integrated into one or more integrated circuit chips, not shown. For example, the pulse generators TX-j_, the switches SWTX-j_ and SWRX-j_, the DC-DC converter 101, the bias circuit 117, and the bias switch SWp are integrated in the same first circuit chip integrated, and the reception circuit 105 and the control circuit 103 are integrated in the same second integrated circuit chip. However, the embodiments described are not limited to this particular case.
    In the example of FIG. 1, the control circuit 100 comprises a single reception circuit 105 shared by the various transducers TD] _, ..., TD n . In this case, several successive ultrasonic shots can be taken to acquire an image of the body to be analyzed. An example of how the system works is as follows. During a first ultrasonic emission phase, the switches SWTX] _, ..., SWTX n are all closed (set to on), and the control circuit 103 simultaneously controls the pulse generators TX] _, ... TX n to apply excitation signals to the different transducers. For this, the control circuit 103 applies to the input of each pulse generator TX-j_ a predetermined logic sequence (or bit stream), representative of the excitation signal to be applied to the transducer TD-j_. This logic signal is converted by the generator TX-j_ into a pulse train of level + HV / -HV, applied to the electrode E2 of the transducer TD-j_ via the switch SWTX-j_. By way of example, the natural frequency, that is to say the main resonant frequency of the TD-j_ ultrasonic transducers, is between 10 and 50 MHz, for example of the order of 30 MHz. The cadence of the logic sequence applied to the input of the pulse generator TX-j_, and therefore of the pulse train applied to the transducer TD-j_, is preferably greater than four times the natural frequency of the transducer TDi, so to be able to ensure good spectral coverage in
    B15246 transmission, for example 120 MHz for a 30 MHz transducer. At the end of the transmission phase, the switches SWTXy, SWTX n are open (blocked), and a first reception switch SWRXy is closed, the other reception switches being kept open. The response signal generated by the transducer TDy is then read and digitized via the reception circuit 105 during a first reception phase. This signal can be memorized by the control circuit 103. The transmission and reception phases are then reiterated by scanning, on reception, the various transducers TDy, TD n , that is to say by modifying each iteration l address of the reception switch SWRXy controlled in the closed state during the reception phase. The control of the transmit switches SWTXy and receive SWRXy is for example carried out through the control circuit 103.
    As a variant (not shown), the control circuit 100 comprises n reception circuits 105y, 105 n identical or similar to the circuit 105 described above, connected respectively to the n terminals ay, a n . In this case, the reception switches SWRXy,. . . SWRX n can be omitted, each reception channel 105-j_ having its input node c connected to the corresponding terminal ay. In this variant, the return signals received by the n transducers can be read simultaneously. Thus, an image of the object to be analyzed can be obtained after a single cycle of transmission / reception of ultrasound by the transducers.
    In another variant, the control circuit 100 comprises a number r of intermediate reception circuits between 1 and n, which makes it possible to acquire an image of the object after n / r ultrasound transmission / reception cycles.
    FIG. 2 is an electrical diagram illustrating in more detail an exemplary embodiment of a TXy pulse generator of the control circuit 100 of FIG. 1. In this example, the TXy pulse generator is a push-type assembly. jumper based on MOS transistors. More particularly, the TXy pulse generator of FIG. 2 comprises a channel MOS transistor
    B15246
    P 201 and an N-channel MOS transistor 203. The transistor 201 has its source (s) connected to a node for applying the high supply voltage + HV of the generator and its drain (d) connected to the drain (d) of transistor 203. Transistor 203 has its source (s) connected to a node for applying the low supply voltage -HV of the generator. The gate (g) of the transistor 201 is also connected to the gate (g) of the transistor 203. The input node in of the pulse generator TX-j_ is connected to the node common to the gates of the transistors 201 and 203, and the output node out of the pulse generator TX-j_ is connected to the node common to the sources of the transistors 201 and 203.
    As a variant, a similar arrangement can be achieved by replacing the transistor 201 by a bipolar transistor of the NPN type and the transistor 203 by a bipolar transistor of the PNP type.
    FIG. 3 is an electrical diagram illustrating in more detail another embodiment of a pulse generator TX-j_ of the control circuit 100 of FIG. 1.
    In this example, the pulse generator TX-j_ comprises two controlled switches 251 and 253, for example MOS transistors or bipolar transistors, connected in series between a node for applying the low supply voltage -HV of the generator , and a node for applying the high supply voltage + HV of the generator. More particularly, in the example shown, the switch 251 has a first conduction node connected to the node -HV and a second conduction node, and the switch 253 has a first conduction node connected to the second conduction node of the switch 251 and a second conduction node connected to the + HV node. The TX-j_ pulse generator further comprises two diodes 255 and 257 connected in antiparallel between the midpoint between the switches 251 and 253 and the output node out of the generator. More particularly, in the example shown, the diode 255 has its anode connected to the common conduction node between the switches 251 and 253 and its cathode connected to the out node, and
    B15246 the diode 257 has its anode connected to the out node and its cathode connected to the common conduction node between the switches 251 and 253. The pulse generator TX-j_ of FIG. 3 further comprises a controlled switch 259, for example a MOS transistor or a bipolar transistor, connecting, by its conduction nodes, the midpoint between switches 251 and 253 to the reference node GND, and a controlled switch 261, for example a MOS transistor or a bipolar transistor, connecting, by its conduction nodes, the out node at the GND node. The pulse generator TX-j_ further comprises a logic circuit 263 with three binary inputs el, e2, e3 and three binary outputs si, s2, s3, s4. The outputs si, s2, s3 and s4 of the circuit 263 are respectively connected to the control nodes of the switches 253, 255, 261 and 259 to control these transistors. In this example, the logic signal in control of the pulse generator TX-j_, supplied by the control circuit 103 of FIG. 1, is a three-bit signal inl, in2, in3, the bits inl, in2, in3 being respectively applied to the inputs el, e2, e3 of the logic circuit 263 of the generator. More particularly, the binary signal inl is a logic signal for controlling the switch 253, the binary signal in2 is a logic signal for controlling the switch 251, and the binary signal in3 is a command signal for the switch 261 .
    The logic circuit 2 63 has the role of transposing the logic signals inl, in2, in3, supplied by the control circuit 103, into effective control signals of the switches 251, 253, 259 and 261 of the pulse generators TX-j_ .
    More particularly, in the transmission or excitation phase, the control circuit 103 applies to the node e3 of the circuit 263 a signal in3 for controlling the opening of the switch 261. The logic circuit 263 then commands, via its node output s3, the opening of the switch 261. The switches 253 and 251 are controlled, via the nodes si and s2, depending on the state of the signals inl and in2. More particularly, circuit 263 directly transmits the signals
    B15246 input inl and in2 on its output nodes si and s2. In the transmission phase, the circuit 263 also controls the switch 259 via its output node s4, so that the switch 259 is open when at least one of the switches 251 and 253 is closed and is closed when the switches 251 and 253 are both open.
    In the reception phase, the control circuit 103 applies to the node e3 of the circuit 263 a signal in3 for controlling the opening of the switch 261. The logic circuit 263 then controls, via its output node s3, the opening of the switch 261, and, via its output node s4, the closing of switches 259. The switches 259 and 261 remain closed and open respectively regardless of the state of the input signals inl and in2 applied to the nodes input el and e2 of circuit 263.
    In this example, the diodes 255 and 257 form, in reception phase, a potential barrier for the return signals generated by the transducers, so as to prevent part of the power of the return signal from being lost in the generator d 'impulses.
    For example, the logical function f implemented by circuit 263, such as {si, s2, s3, s4} = f ({el, e2, e3}), is defined by the following truth table:
    opening, and where the value x can be indifferently equal to 1 or to 0.
    FIGS. 4A, 4B and 4C are electrical diagrams illustrating in more detail three alternative embodiments of
    B15246 the reception amplifier 107 (LNA) of the control circuit 100 of FIG. 1.
    FIG. 4A illustrates a first exemplary embodiment of the amplifier 107. In this example, the amplifier 107 is an amplifier of the trans impedance type. It includes an operational amplifier 301 whose inverting input (-) is connected to the output via a resistor Rf. The inverting input of the operational amplifier 301 is connected to the input of the amplifier 107, and the output of the operational amplifier 301 is connected to the output of the amplifier 107. The non-inverting input (+) of the operational amplifier 301 is connected to the reference node GND of the circuit.
    FIG. 4B illustrates another exemplary embodiment of the amplifier 107. In this example, the amplifier 107 is a buffer type amplifier. It comprises an operational amplifier 301, the inverting input (-) of which is connected on the one hand to the reference node GND via a resistor RI, and on the other hand to its output via a resistance R2. The non-inverting input (+) of the operational amplifier 301 is connected to the input of the amplifier 107, and the output of the operational amplifier 301 is connected to the output of the amplifier 107.
    FIG. 4C illustrates another exemplary embodiment of the amplifier 107. In this example, the amplifier 107 is an amplifier of the charge amplifier type. It comprises an operational amplifier 301, the inverting input (-) of which is connected on the one hand to the input of the amplifier 107 by means of a resistor RI, and on the other hand to its output by the through a resistor R2 and a capacitor C connected in parallel with the resistor R2. The non-inverting input (+) of the operational amplifier 301 is connected to the reference node GND of the circuit. The output of the operational amplifier 301 is connected to the output of the amplifier 107.
    The choice of the type of amplifier 107 from the assemblies of FIGS. 4A, 4B and 4C can be made as a function of
    B15246 the impedance of the ultrasonic transducers intended to be controlled by the circuit 100. In particular, the assemblies of FIGS. 4A and 4C are particularly suitable for transducers having high impedances, for example greater than 2 kQ, while the assembly of the FIG. 4B is suitable for transducers of lower impedance, for example of the order of 200 Ω at 2 kQ. By way of example, the reception circuit 105 of the control circuit 100 may comprise several different reception amplifiers 107, and a multiplexing circuit configurable to select the reception amplifier 107 to be used according to the type of transducers used.
    FIG. 5 is an electrical diagram illustrating an alternative embodiment of the reception circuit 105 of the control circuit 100 of FIG. 1. In the example shown, for the sake of simplification, the impedance matching circuit 111, the circuit gain adjustment 113, and the anti-aliasing filter 115 have not been shown.
    The reception circuit 105 of FIG. 5 differs from the reception circuit 105 of FIG. 1 mainly in that it further comprises, between the amplifier 107 and the analog-to-digital converter 109, a network of switched capacities 401 making it possible to store analogically samples of the output signal of the amplifier 107, before their digitization by the converter 109. An advantage of the variant of FIG. 5 is that it makes it possible to reduce the operating frequency of the analog to digital converter 109, and therefore the electrical power consumed by the converter.
    In the example shown, the switched capacitance network 401 comprises K capacitors Cj_, ..., Cpp with K integer greater than 1, and, for each capacitor Cj, with j integer ranging from 1 to K, a write switch Wj connecting a first electrode of the capacitor to the output of the amplifier 107, and a read switch Rj connecting the second electrode of the capacitor to the input of the analog-to-digital converter 109. The switches Wj and Rj are for example controlled by the
    B15246 control circuit 103. In operation, samples of the analog output signal of the amplifier 107 are successively stored in the different capacities Cj of the network 401, at the desired sampling frequency of the electrical response signal produced by the connected transducer to the receiving circuit. These analog samples are then successively digitized by the analog digital converter 109, at a frequency lower than the sampling frequency of the analog signal. By way of example, the number K of capacities of the capacity network 401 is equal to the number of samples of the electrical response signal which it is desired to acquire during a sequence of transmission / reception of ultrasonic waves.
    In the case where the reception circuit 105 comprises at least one of the elements 113 and 115 (FIG. 1), the network of switched capacities 401 can be arranged downstream of these elements, that is to say between these elements and the analog converter digital 109.
    In the case where the control circuit 100 comprises several reception channels 105, each reception channel may comprise a network of switched capacities 401 of the type described in relation to FIG. 5.
    Particular embodiments have been described. Various variants and modifications will appear to those skilled in the art. In particular, the embodiments described are not limited to the numerical examples of operating frequencies and / or of voltage level mentioned in the description.
    Furthermore, it will be noted that the embodiments described above can be adapted whatever the arrangement of the ultrasonic transducers to be controlled. In particular, the embodiments described are compatible with arrangements in a linear strip or in a matrix of the ultrasonic transducers.
    In addition, in the embodiments described above, the control circuit 100 can be used to
    B15246 controlling associations in parallel of several ultrasonic transducers. More particularly, in the example of FIG. 1, several ultrasonic transducers connected in parallel can be connected between each individual control terminal 5 al and the common terminal b of the control circuit 100.
    B15246
    权利要求:
    Claims (12)
    [1" id="c-fr-0001]
    1. Control circuit (100) of ultrasonic transducers (TD] _, TD n ), characterized in that it is configurable as a function of the type of transducers to be controlled.
    [2" id="c-fr-0002]
    2. Circuit (100) according to claim 1, comprising a first terminal (b) intended to be connected to a first electrode (El) of each of the transducers (TD] _, ..., TD n ), and a switch polarization (SWp) configurable to connect the first terminal (b) to either of the first (PI) and second (P2) polarization nodes depending on the type of transducers to be controlled.
    [3" id="c-fr-0003]
    3. The circuit (100) according to claim 1, in which the first bias node (PI) is an output node of a circuit (117) for supplying a DC bias voltage (Vbias) ' e t in which the second polarization node (P2) is a node (GND) for applying a reference potential of the circuit (100).
    [4" id="c-fr-0004]
    4. The circuit (100) according to claim 3, in which the circuit (117) for supplying a DC bias voltage (Vbias) comprises a DC voltage converter configurable to modify the level of the bias voltage (Vpj_ as ). that it delivers.
    [5" id="c-fr-0005]
    5. Circuit (100) according to any one of claims 1 to 4, comprising a plurality of second terminals (aj_, ..., a n ) intended to be connected respectively to second electrodes (E2) of the transducers (TD] _, ..., TD n ) to order.
    [6" id="c-fr-0006]
    6. Circuit (100) according to claim 5, comprising a plurality of voltage pulse generators (TXi, ..., TX n ), each of the second terminals (ay ..., a n ) being connected to the one of the voltage pulse generators.
    [7" id="c-fr-0007]
    7. The circuit (100) according to claim 6, in which the voltage level of the voltage pulses delivered by the pulse generators (TX] _, ..., TX n ) is configurable.
    B15246
    [8" id="c-fr-0008]
    8. Circuit (100) according to any one of claims 5 to 7, further comprising a reception circuit (105) comprising an input node (c), a reception amplifier (107) whose input is connected at the input node (c), an analog-digital converter (109) whose input is connected to the output of the reception amplifier (107), and an output (d) connected to the output of the analog-to-digital converter ( 109).
    [9" id="c-fr-0009]
    9. The circuit (100) according to claim 8, comprising a plurality of switches (SWRX] _, ... SWRX n ) respectively connecting the second terminals (aj_, ..., a n ) to the input node (c ) of the receiving circuit.
    [10" id="c-fr-0010]
    10. The circuit (100) according to claim 8 or 9, wherein the reception circuit (105) comprises an impedance matching circuit (111) configurable as a function of the type of transducers to be controlled.
    [11" id="c-fr-0011]
    11. The circuit (100) according to claim 8, in which the reception circuit (105) further comprises, between the reception amplifier (107) and the analog-digital converter (109), at minus one of the following:
    an analog gain adjustment circuit (113); and an analog anti-aliasing filter (115).
    [12" id="c-fr-0012]
    12. Circuit (100) according to any one of claims 8 to 11, in which the reception circuit (105) comprises a network (401) of switched capacities arranged upstream of the analog-digital converter (109), making it possible to store analog samples representative of the output signal of the reception amplifier (107), prior to their digitization by the analog-digital converter (109).
    B 15246
    1/3
    100
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    同族专利:
    公开号 | 公开日
    CA3049169A1|2018-07-12|
    US20190337014A1|2019-11-07|
    EP3566308A1|2019-11-13|
    WO2018127655A1|2018-07-12|
    CN110301093A|2019-10-01|
    JP2020503814A|2020-01-30|
    FR3061616B1|2020-10-02|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US20050154300A1|2003-12-30|2005-07-14|Wodnicki Robert G.|Integrated low-voltage transmit/receive switch for ultrasound imaging system|
    WO2009073743A1|2007-12-03|2009-06-11|Kolo Technologies Inc.|Capacitive micromachined ultrasonic transducer with voltage feedback|
    US20110201936A1|2010-02-15|2011-08-18|Kabushiki Kaisha Toshiba|Ultrasound probe|WO2020254325A1|2019-06-18|2020-12-24|Moduleus|Ultrasonic matrix imaging device|
    FR3086063A1|2018-09-13|2020-03-20|Moduleus|ULTRASONIC IMAGING DEVICE|
    FR3086475B1|2018-09-24|2021-05-21|Moduleus|ELECTRONIC CIRCUIT WITH SYNCHRONIZED CLOCK DISTRIBUTION|
    法律状态:
    2018-01-19| PLFP| Fee payment|Year of fee payment: 2 |
    2018-07-06| PLSC| Publication of the preliminary search report|Effective date: 20180706 |
    2020-01-17| PLFP| Fee payment|Year of fee payment: 4 |
    2021-01-29| PLFP| Fee payment|Year of fee payment: 5 |
    2022-01-28| PLFP| Fee payment|Year of fee payment: 6 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1750071A|FR3061616B1|2017-01-04|2017-01-04|ULTRASONIC TRANSDUCER CONTROL CIRCUIT|
    FR1750071|2017-01-04|FR1750071A| FR3061616B1|2017-01-04|2017-01-04|ULTRASONIC TRANSDUCER CONTROL CIRCUIT|
    US16/475,490| US20190337014A1|2017-01-04|2018-01-02|Control circuit for ultrasonic transducers|
    CN201880010081.XA| CN110301093A|2017-01-04|2018-01-02|Control circuit for ultrasonic transducer|
    EP18701511.0A| EP3566308A1|2017-01-04|2018-01-02|Control circuit for ultrasonic transducers|
    PCT/FR2018/050003| WO2018127655A1|2017-01-04|2018-01-02|Control circuit for ultrasonic transducers|
    JP2019537069A| JP2020503814A|2017-01-04|2018-01-02|Control circuit for ultrasonic transducer|
    CA3049169A| CA3049169A1|2017-01-04|2018-01-02|Control circuit for ultrasonic transducers|
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